The present invention relates generally to transferring data between a peripheral device and a processor of a data processing system. More particularly, the invention is directed to a method, and apparatus for implementing that method, for conducting a data transfer cycle to transfer data between the processor unit and the peripheral device that depends upon the activity of the other device controllers, permitting much higher actual data rates, yet giving access for data transfers to lower priority peripheral devices.
Today's data processing systems are capable of processing huge amounts of data. This data, however, is not stored in the primary storage area (i.e., memory) of the processor unit itself, but rather in a secondary storage area usually in the form of such peripheral devices such as tape devices, disk drive devices, and the like. Data processing systems will typically include at least one or more processor units connected by an input/output (I/O) bus, to a plurality of device controllers which, in turn, couple the I/O bus to peripheral devices (i.e.. the aforementioned tape and disk devices, as well as printers, communication devices, and the like).
As is well known, certain peripheral devices (e.g., disk devices) are capable of transferring data at a much higher data rate than other peripheral devices (e.g. communication devices. printers, etc.). When a number of peripheral devices, and in particular a number of varying types of peripheral devices, are coupled (via device controllers) to the I/O bus it is undesirable to have one peripheral device tie up the I/O bus in a data transfer cycle that excludes the other peripheral devices; the result can be a loss of data. For example, the device controller that connects a peripheral device to the I/O bus typically can include buffering (temporary storage) to temporarily hold data that is to be transferred from the controlled peripheral device to the processor unit in the event the I/O bus is being utilized by another device controller/peripheral device combination. If, however, this other peripheral device takes too long to transfer data, the device controller awaiting access to the I/O bus may experience a data overrun (i.e.. the buffer receives more data than it can handle, resulting in the loss of data).
One solution to avoiding the data overrun problem is to allow data transfers to occur in short bursts or blocks of a limited number of data words, after which the peripheral device gives up, and is precluded from, access to the I/O bus until sufficient time has elapsed to permit other peripheral devices access. This ensures that data can be transferred by all of the devices, and avoids any data overrun problems.
However, a drawback to this solution is that the effective data rate is substantially lowered due to the "overhead" of a data transfer cycle (which includes the time of preclusion from access to the I/O bus following a data word block transfer--sometimes also called "hold-off" periods). Data transfers comprising transmission of a number of small data word blocks, each accompanied by a hold-off period that is sometimes larger than the transfer time itself, result in an effective data transfer rate that is much less than nominal--even when only one peripheral device is involved in the data transfer.
Of course, trade-offs can be achieved by increasing the amount of temporary storage available in each device controller for buffering, increasing the data word blocks that are transferred each burst period, and decreasing the hold-off periods. Given a specific mix of peripheral devices coupled to a processor unit by an I/O bus, an optimum data rate can be achieved by manipulating these variables. Unfortunately, this will solidify the system configuration, and any attempt to change the configuration by either upgrading or adding additional device controllers seriously affects the overall system performance.